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www.irf.com 1 high reliability radiation hardened low power dc-dc converter ML1000605D description total dose > 100 krad(si) see > 82 mev . cm 2 /mg low weight < 50 grams 97v to 103v dc input range o/p 1: +6.0v (up to 500ma) o/p 2: -5.0v (up to 100ma) output ripple: < 1mvrms (100hz - 50mhz) cs rejection input to outputs: > 90db (50hz - 1.0mhz) 10m ? @ 100vdc isolation input under-voltage protection meets conducted emission requirements of major power buses: 100hz - 100khz: 80dbuarms 100khz - 10mhz: -20db/decade 10mhz - 50mhz: 40dbuarms short circuit and overload protection meets derating requirements of eee-inst 002 and ecss-q-30-11a isolated on/off control via high level pulse command (latching relay) status telemetry (relay contact type) workmanship per ipc-a610 class 3 board is coated with arathane-5750 features 100v input, dual output applications the ml-series of isolated dc-dc converters for space applications are low power radiation hardened high reliability devices designed for hostile radiation environments such as those encountered by geostationary earth orbit satellites, deep space probes and communication systems. features include small size, high efficiency, low weight, and a good tolerance to total ionizing dose, single event effects, and environmental stresses such as temperature extremes, mechanical shock, and vibration. all components are fully derated to meet the requirements of eee-inst-002 (nasa) and ecss-q- 30-11a (esa). extensive documentation including worst case analysis, radiation susceptibility, thermal analysis, stress analysis, and reliability analysis are available. the ml-series converter has two outputs ? one positive and one negative - each is independently regulated via linear post regulators. the outputs are sequenced during turn-on and turn-off such that negative output comes up first at turn-on and stays up at turn-off until the positive output has decreased. the ml-series converters incorporate a fixed frequency flyback power converter and internal emi filter that meets the requirements for most major satellite power buses. the converter includes isolated on/off telecommand with associated status telemetry. the converter also includes input under voltage shut-down functionality. due to the linear post regulation of the outputs, the ml- series is well suited for use in rf-applications where low noise, high output voltage accuracy, and high cs attenuation is required. each converter is provided as a complete board assembly for installation into the host equipment chassis. the board is conformal coated (except for mating surfaces) and is mounted in the host chassis using screws. the board outline is l x w x h: 70mm x 50mm x 18mm. the weight is less than 50 grams. low power rf systems (like lna) on-board satellites non-flight versions of the ml-series converters are available for system development purposes. variations in electrical specifications and screening to meet custom requirements can be accommodated. pd-97806
2 www.irf.com ML1000605D (100v input, dual output) circuit description an under-voltage protection circuit prohibits the converter from operating when the line voltage is too low for safe operation. in case of an under voltage event the converter will not start when the input voltage returns to its nominal level before an off-command followed by an on-command has been issued. the isolated on/off telecommand is made with a latching relay and is intended for use with a 26v pulse command. a status telemetry derived from a spare set of contacts in the relay is used for status telemetry. design methodology the ml-series is developed using a proven conservative design methodology, which includes selecting radiation tolerant, and established reliability components and full derating to the requirements of eee-inst-002 and ecss-st-11a. the ml-series converters utilize two-stage regulation with a flyback topology with a switching frequency of 140khz for primary regulation and linear post regulation for each of the outputs. the output power is limited under any load fault condition to approximately 120% of rated output. an overload condition on the positive output causes the converter output to behave like a constant current source with the output voltage dropping below nominal. an overload condition at the negative output causes the positive output to shut-down in order to protect rf-transistors in the load. the converter will resume normal operation when the load current is reduced below the current limit point. for further information please refer to the ml-series generic description available at www.irf.com .
www.irf.com 3 ML1000605D (100v input, dual output) electrical performance characteristics for notes to specifications, refer to page 5 specifications * meets full derating input voltage range -0.5vdc to +120vdc input voltage range (note 9) +97vdc to +103vdc output power internally limited output power 0 to max. rated operating mounting point -55c to +100c operating mounting point -40c to +75c * temperature (note 10) temperature (note 9) storage temperature -55c to +125c cold start temperature -55c recommended operating conditions absolute maximum ratings limits parameter condition conditions -40 c tc +75 c v in = 100v dc 0.5%, c l = 0f unless otherwise specified min nom max unit primary input voltage 97 100 103 v output voltage ( v out ) (o/p 1, o/p 2) +6.0v -5.0v +6.0v -5.0v +6.0v -5.0v 1 1 2 2 3 3 note 1 0% i out 100% of rated load 0% i out 100% of rated load 0% i out 100% of rated load +5.970 -4.975 +5.940 -4.950 +5.880 -4.900 +6.00 -5.00 +6.030 -5.025 +6.060 -5.050 6.120 5.100 v v v output power ( p out ) (o/p 1, o/p 2) +6.0v -5.0v 1,2,3 v in = 97, 100, 103v 3.0 0.5 w output current ( i out ) (o/p 1, o/p 2) +6.0v -5.0v 1,2,3 v in = 97, 100, 103v 0 0 500 100 ma line regulation ( vr line ) each output 1,2,3 v in = 97, 100, 103v i out = 10%, 50%, 100% rated -1.0 1.0 mv load regulation ( vr load ) each output 1,2,3 i out = 10%, 50%, 100% rated v in = 97, 100, 103v -1.0 1.0 mv cross regulation ( vr cross ) 1,2,3 v in = 97, 100, 103v, note 1 1.0 mv input current 1,2,3 i out = 0, commanded on commanded off 10 15 2.0 ma switching frequency ( f s ) 1,2,3 notes 1, 7 126 140 154 khz input under voltage trig level 1,2,3 0% i out 100% of rated load 85 95 v output sequencing turn-on delay o/p 2 to o/p 1 turn-off delay o/p1 to o/p 2 1,2,3 i out 20% for output 1 2.0 1.0 12 8.0 ms
4 www.irf.com ML1000605D (100v input, dual output) electrical performance characteristics (continued) for notes to specifications, refer to page 5 limits parameter condition conditions -40 c tc +75 c v in = 100v dc 0.5%, c l = 0f unless otherwise specified min nom max unit output ripple ( v rip ) each output +6.0v -5.0v +6.0v -5.0v 1 1,2 v in = 97, 100, 103v i out = 100% rated load frequency domain 100hz ? 50mhz note 1 time domain 100hz ? 50mhz notes 1, 2 1.0 1.0 30 30 mvrms mvpp efficiency ( e ff ) for combined output power of 0.70w 1.75w 3.50w 1,2,3 i out = 20% rated load i out = 50% rated load i out = 100% rated load 37 52 60 38 54 62 % telecommand i/f pulse voltage high pulse voltage low pulse duration 1,2,3 note 1 +22 -40 10 +30 0.5 1000 v v ms telemetry converter on converter off 1,2,3 400 1.0 422 450 ohm mohm current limit point each output +6.0v -5.0v 1,2,3 v out = 100mv below nominal 550 110 700 150 ma output response to step load changes ( v tld ) +6.0v -5.0v 1,2,3 20% to / from 100% load, note 3 -70 -50 70 50 mv pk recovery time, step load changes ( t tld ) +6.0 -5.0 1,2,3 20% to / from 100% load , notes 3, 4 2.5 2.5 ms turn-on response overshoot ( v os ) +6.0v -5.0v turn-on delay 1,2,3 10% load, full load note 5 2.0 60 50 10 mv ms capacitive load ( c l ) +6.0v -5.0v 1 i out = 100% rated load no effect on dc performance notes 1, 6 each output 100 100 f
www.irf.com 5 ML1000605D (100v input, dual output) electrical performance characteristics (continued) notes: specification and electrical performance characteristics tables 1. parameter is tested as part of design characterization or after design changes. thereafter, parameter shall be guaranteed to the limits specified. 2. guaranteed for a d.c. to 50mhz bandwidth. tested using a 10.7mhz bandwidth. 3. load current step transition time 10 s. 4. recovery time is measured from the initiation of the transient to where v out has returned to within 1% of its steady state value. 5. turn-on delay time from application of telecommand pulse to the point where output 2 = 98% of nominal output voltage. 6. capacitive load may be any value from 0 to the maximum limit without compromising the output sequencing performance. a capacitive load in excess of the maximum limit may influence the output sequencing performance and start-up time, converter operation and dc performance will remain intact. 7. the switching frequency and 1st and 2nd harmonic of the input ripple is tested on every unit. 8. mil-hdbk-217f2 stress-dependent method is used with 2 exceptions: for soldering a fixed failure rate at 0.035fit is used and for power mosfets the dissipated power (instead of rated power) is used for the pr parameter. 1 fit is 1 failure in 10 9 hours. 9. the converter meets full derating per eee-inst-002 and ecss-q-30-11a with the following exception: for schottky diode jans1n5819 a maximum derated junction temperature of +110c. for eee-inst-002 it is required that ceramic capacitors with a voltage stress below 10v shall be rated for minimum 100v - in the product such capacitors is rated for 50v minimum. 10. although operation temperatures between -55c to +100c and -40c to+75c is guaranteed, no parameter limits are specified. electrical performance characteristics - definition of conditions condition definition comment 1 bol @ +25c interface temperature initial setting 2 bol @ -40c to +75c interface temperature initial setting and worst case temperature variation 3 eol @ -40c to +75c interface temperature worst case performance including initial setting, temperature variation, aging and radiation degradation limits parameter condition conditions -40 c tc +75 c v in = 100v dc 0.5%, c l = 0f unless otherwise specified min nom max unit emc conducted susceptibility (line rejection) 1 i out = 100% rated load primary power sine wave injection of 2vp-p, 100hz to 1mhz, note 1 96 110 db electroma g netic interference (emi), conducted emission (ce) 1 i out = 100% rated load, notes 1, 7 limits per figures 4 and 5 isolation 1 input to output, any potential to telecommand input and any potential to telemetry output, test @ 100vdc 10 m ? device weight 50 g failure rate mil-hdbk-217f2, sf, 35 c, note 8 60 fits
6 www.irf.com ML1000605D (100v input, dual output) model definition and test plans model description build standard ebb the ebb is an electrical representative model. the ebb is intended to be used by customers in their proto type at equipment level. ebb models are built at ir?s danish design center. the pcb will be hand soldered by the engineering group. no staking and conformal coating is foreseen preferably same type of eee parts as intended for flight, but lower grade will be used for convenience. for resistors and capacitors different types with same basic characteristics may be used eqm the eqm is an electrical and mechanical representative model. the eqm is intended to be used by customer in their eqm at equipment level. flight standard for processes. same type of eee parts as intended for flight, but lower grade may be used for convenience. fm flight standard models. full flight standard model definition test plan - a the ebb must pass the following tests: test no. type of test location* remarks 1 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) ird acceptance test procedure 2 electrical performance test in temperature (q-level) ird acceptance test procedure 3 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) ird acceptance test procedure 4 final inspection ird general inspection procedure
www.irf.com 7 ML1000605D (100v input, dual output) test plan - b test plan - c note: location* - ird: ir?s danish design center, skovlunde, denmark - irsj: ir?s site in san jose, california, usa the eqm must pass the following tests: test no. type of test location* remarks 1 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) irsj acceptance test procedure 2 thermal cycling with electrical monitoring of input and outputs (q-level) irsj acceptance test procedure 10 cycles 3 electrical performance test in temperature (q-level) irsj acceptance test procedure 4 random vibration test in (q-level) external test house vibration test procedure 5 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) irsj acceptance test procedure 6 mechanical measurements irsj acceptance test procedure 7 final inspection irsj general inspection procedure the fm must pass the following tests: test no. type of test location* remarks 1 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) irsj acceptance test procedure 2 electrical performance test in temperature (a-levels) irsj acceptance test procedure 3 electrical performance test, room temperature incl. limited emc test (ce 50khz-1mhz) irsj acceptance test procedure 4 electrical performance test, room temperature irsj acceptance test procedure 5 mechanical measurements irsj acceptance test procedure 6 final inspection irsj general inspection procedure
8 www.irf.com ML1000605D (100v input, dual output) radiation performance tid the tid radiation performance is guaranteed by worst case analysis with radiation degradation data for each radiation sensitive component used in the dc-dc converter. for tid radiation verification testing (rvt) for each wafer lot for all sensitive components is part of the eee parts requirements per table below. component type rvt plan (applicable to all flight lots) jans2n2222a ldrs 0.01 to 0.1 rad up to 200 krad per ir rvt plan jans2n2907a ldrs 0.01 to 0.1 rad up to 200 krad per ir rvt plan jansr2n7492t2 rvt by manufacturer (hdr) irhf57214sescs rvt by manufacturer (hdr) irhlub770z4scs rvt by manufacturer (hdr) irhlub7970z4scs rvt by manufacturer (hdr) lm124awr rvt by manufacturer (eldrs) is2-1009rh rvt by manufacturer (hdr) ldrs 0.01 to 0.1 rad up to 100 krad per ir rvt plan uc1845a ldrs 0.01 to 0.1 rad/s up to 100krad per ir rvt plan tid rvt plan table see the see radiation performance is guaranteed by a combination of derating and mitigation at circuit level. for mitigation at circuit level both theoretical analysis and testing with imposed see effects are performed. the applicable see and mitigation concept is presented in table below. the maximum output perturbation is 5% of the nominal output voltage during any see. component type applicable see mitigation concept rh mosfet segr vds derating in combination with see soa curves from manufacturer data sheet op-amp set, 15us perturbation to rail mitigation at circuit level (filtering) voltage reference set, 10us perturbation to rail mitigation at circuit level (filtering) set, 15us perturbation to rail mitigation at circuit level (filtering) double pulses mitigation at circuit level (filtering, no saturation of magnetic parts) pwm missing pulses mitigation at circuit level (filtering, no saturation of magnetic parts) applicable see and mitigation methods table
www.irf.com 9 ML1000605D (100v input, dual output) eee parts technical standard for component screening and dpa rules, refer to the generic ml-series data sheet at www.irf.com . random vibration fig 1- block diagram grounding and isolation scheme axis frequency range (hz) level psd level (g rms ) duration (s) 20-100 +6 db/oct 100-1600 0.5 sqr(g)/hz x, y, z 1600-2000 -12 db/oct 29.9 180 parameter grounding & isolation performance isolation: primary to secondary: telecommand: status tm: > 10 mohm // < 50nf floating floating grounding: secondary return bound to chassis via multiple screw connections input filter fly-back trans- former rectifier & filter rectifier & filter linear regulator rectifier & filter fly-back power switch pwm controller uvp monitor & lat ch latching relay current shunt start-up resistor negative linear regulator primary power bus tc on tc off on/off tm disable int.supply v1: +6v 500ma v2: -5v 100ma rectifier & filter internal aux output sequencing
10 www.irf.com ML1000605D (100v input, dual output) interface schematics fig 2 - power input: l1 l3 l2 r1 c1 c8 c6 r4 primary power bus j1 3 1 c9 c7 11 9 primary power bus return to fly-back converter and star tup c ir cuit cr1 primary power bus primary power bus return component component type package value voltage (v) c1 br40 ii radial 0.56 f 200 c6 cdr33bx smd 1210 27nf 100 c7 cdr33bx smd 1210 27nf 100 c8 cdr33bx smd 1210 27nf 100 c9 cdr33bx smd 1210 27nf 100 cr1 1n5806us a- mflf 2.5a 150 l1 r6.3 toroid 2 x109.8 h l2 high flux toroid 90 h l3 high flux toroid 30 h r1 rwr81s rwr 9.09ohms 500 r4 rm1206b smd 1206 21.5ohms 100
www.irf.com 11 ML1000605D (100v input, dual output) fig 3 - tm / tc interface: cr201 cr202 cr203 cr204 cr207 cr208 r201 r202 on off 4 10 9 5 k1 8 3 7 6 1 2 j1 cr206 cr205 tc on tc on return tc off return tc off 13 6 7 14 8 15 status tm status tm return cr214 cr213 r218 r223 r219 r220 from input filter vr101 c103 from primary aux. u101 pwm vc relay is shown on r203 component component type package value voltage (v) cr201 1n6640us d-5d 0.3a 75 cr202 1n6640us d-5d 0.3a 75 cr203 1n6640us d-5d 0.3a 75 cr204 1n6640us d-5d 0.3a 75 cr205 1n6640us d-5d 0.3a 75 cr206 1n6640us d-5d 0.3a 75 cr207 1n6640us d-5d 0.3a 75 cr208 1n6640us d-5d 0.3a 75 cr213 1n6640us d-5d 0.3a 75 cr204 1n6640us d-5d 0.3a 75 c103 cwr29 smd h 33 f 25 k201 j422-26m shoc to-5 26.5 r118 rm1206b smd 1206 21.5kohms 100 r119 rm1206b smd 1206 21.5kohms 100 r120 rm1206b smd 1206 21.5kohms 100 r123 rm1206b smd 1206 21.5kohms 100 r201 rm1206b smd 1206 215ohms 100 r202 rm1206b smd 1206 215ohms 100 vr101 1n4109ur-1 do-213aa 15
12 www.irf.com ML1000605D (100v input, dual output) emi performance fig 4 - typical conducted emission performance at power input: fig 5 - typical conducted emission performance at output 1:
www.irf.com 13 ML1000605D (100v input, dual output) fig 6 - typical power conversion efficiency vs +6v output current parametric power conversion efficiency 35% 40% 45% 50% 55% 60% 65% 0.10a 0.15a 0.20a 0.25a 0.30a 0.35a 0.40a 0.45a 0.50a +6v output current typical efficiency, vin 100v, i/f temperature +75c 0.020a 0.050a 0.100a with -5v output current
14 www.irf.com ML1000605D (100v input, dual output) recommended mounting stud design it is foreseen with a mounting stud design with circular mounting studs made out of aluminum with a diameter of 4.0mm and a treaded hole support mounting with m2 screws. 5pcs m2 screws are used for mounting the board. mounting torque shall be 30ncm 5.0ncm.
www.irf.com 15 ML1000605D (100v input, dual output) mechanical interface
16 www.irf.com ML1000605D (100v input, dual output) pin designation tables thermal design information the thermal design for the ml-series is solely based on heat conduction through the mounting interfaces/mounting screws into the host equipment chassis. the maximum power loss during normal operation is 2.0w. the temperature profile for the board based on all screw mounting points kept at isothermal level is given below. pin # pin # function 1 input power return 9 input power return 2 rerserved 10 rerserved 3 input power 11 input power 4 chasis (ground) 12 voltage tm 5 chasis (ground) 13 tc on return 6tc on 14 tc off return 7tc off 15 tm status return 8 tm status indent.: input terminals (solder, pins, straight) input terminals assignment list pin # pin # function 1 2 v1 (positive output) 3 4 chasis (ground) 5 6 chasis (ground) 7 8 v2 (negative output) output terminals assignment list indent.: output terminals (solder pads)
www.irf.com 17 ML1000605D (100v input, dual output) part numbering world headquarters: 101 n, sepulveda blvd., el segundo, california 90245, usa tel: (310) 252-7105 ir san jose: 2520 junction avenue, san jose, california 95134, usa tel: (408) 434-5000 ir denmark: literbuen10c, dk-2740 skovlunde, denmark, tel: +45 4457 5010 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 04/2013 application information standard documentation

user?s manual end item data package with coc, applicable configuration, mip photo and test results design justification documentation the following documentation can be made available upon request: worst case analysis parts stress analysis thermal analysis mechanical analysis fmeca reliability assessment declared components list declared materials list declared process list output 1 model nominal input voltage 100 = 100v 06 = 6v number of outputs d = dual outputs quality level ebb = elegant bread board model eqm = engineering qualification model blank = fight model ml-series output 2 05 = 5v ml 100 06 05 d /xxx

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